Reduced IP Core×メティエ - List of Manufacturers, Suppliers, Companies and Products

Enlarge/Reduce IP Core (Verilog)

Enlarge/Reduce IP Core (Verilog)

P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024, and the scaling ratio is N/M where N and M can be 1, 2, 3, 4, 5, 6, 7, or 8.

• Company：メティエ
• Price：Other

• Other semiconductors